Altera Cyclone 10 is a family of field-programmable gate arrays (FPGAs) offering a low-power, cost-effective solution for various applications. The Intel Cyclone 10 family includes two device families, Cyclone 10 LP, and Cyclone 10 GX, each optimized for different use cases.
The Intel Cyclone 10 LP family is designed for low-power, cost-sensitive applications that require a balance of power and bandwidth. It features up to 220K logic elements, 6.4 Gbps transceivers, and 1,600 Mbps DDR3 memory support. It also offers integrated intellectual property (IP) such as ARM Cortex-M1 processor, analog-to-digital converter (ADC), and digital signal processing (DSP) blocks.
The Cyclone 10 GX family is optimized for high-performance applications that require higher bandwidth. It features up to 220K logic elements, 12.5 Gbps transceivers, and 2,666 Mbps DDR4 memory support. Altera Cyclone 10 also offers advanced processing capabilities with up to two ARM Cortex-A9 processors, hard floating-point DSP blocks, and a range of configurable I/O standards.
Overall, Altera Cyclone 10 FPGAs offer a versatile and flexible solution for various applications such as industrial automation, smart vision, and automotive. They provide low-power, cost-effective, and high-performance options that can be customized to meet specific requirements.
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Altera® Cyclone® 10 GX FPGA |
Altera® Cyclone® 10 LP FPGA |
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Altera Cyclone 10 GX FPGAs are designed to deliver high-bandwidth performance for applications such as machine vision, video connectivity, and smart vision cameras. |
Altera Cyclone 10 LP FPGAs are optimized for low power consumption and cost-sensitive applications. |
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Altera® Cyclone® 10 LP FPGAs Product Table
| PRODUCT LINE | 10CL006 | 10CL010 | 10CL016 | 10CL025 | 10CL040 | 10CL055 | 10CL080 | 10CL120 | ||||||
| Resources | Logic elements (LEs)1 | 6,000 | 10,000 | 16,000 | 25,000 | 40,000 | 55,000 | 80,000 | 120,000 | |||||
| M9K memory blocks | 30 | 46 | 56 | 66 | 126 | 260 | 305 | 432 | ||||||
| M9K memory size (Kb) | 270 | 414 | 504 | 594 | 1,134 | 2,340 | 2,745 | 3,888 | ||||||
| DSP Blocks (18 x 18 multipliers) | 15 | 23 | 56 | 66 | 126 | 156 | 244 | 288 | ||||||
| Phase-locked loops (PLL) | 2 | 2 | 4 | 4 | 4 | 4 | 4 | 4 | ||||||
| I/O and Architectural Features | Global clock networks | 10 | 10 | 20 | 20 | 20 | 20 | 20 | 20 | |||||
| Maximum user I/O pins | 176 | 176 | 340 | 150 | 325 | 321 | 423 | 525 | ||||||
| Maximum LVDS channels | 65 | 65 | 137 | 52 | 124 | 132 | 178 | 230 | ||||||
| Package Options and I/O Pins: General-Purpose I/O (GPIO) Count, LVDS Pairs | ||||||||||||||
| M164 pin (8 mm x 8 mm, 0.5 mm pitch) | 101,26 | 87, 22 | ||||||||||||
| U256 pin (14 mm x 14 mm, 0.8 mm pitch) | 176, 65 | 176, 65 | 162, 53 | 150, 52 | ||||||||||
| U484 pin (19 mm x 19 mm, 0.8 mm pitch) | 340, 137 | 325, 124 | 321, 132 | 289, 110 | ||||||||||
| E144 pin (22 mm x 22mm, 0.5 mm pitch) | 88, 22 | 88, 22 | 78, 19 | 76, 18 | ||||||||||
| F484 pin (23 mm x 23 mm, 1.0 mm pitch) | 340, 137 | 325, 124 | 321, 132 | 289, 110 | 277, 103 | |||||||||
| F780 pin (29 mm x 29 mm, 1.0 mm pitch) | 423, 178 | 525, 230 | ||||||||||||
Numbers indicate GPIO count, LVDS pairs